The semiconductor has been developed for four decades from the birth of the first semiconductor device. For performing more complicate operations with higher speed, more and more devices and connections are being formed within integrated circuits. The density of semiconductor chips are raised to include more devices and functions in a single chip. In the integrated circuits, a great number of devices and connections are fabricated on a single chip. Various kinds of devices like transistors, resistors, and capacitors are formed together. Each device must operate with good connections to provide interaction between each other for enabling the functionality and the operation of the circuits, especially under the higher and higher packing density of integrated circuits.
Connections must be formed in addition to these densely arranged devices for finishing a circuit to perform operations. In the semiconductor manufacturing process, metallization is a process to form connections between devices. With more and more devices on a chip with high integrity, early stage single layer metallization process had been improved to form multiple layer of connections. Two layers, three layers, or even four layers of connections are formed in present applications. With the sub-micrometer or even smaller devices, the metallization process is challenged with forming narrower conductive lines with compromising resistance and high yield. More layers of defect-free connections must be formed with low production cost and reduced thermal budget.
For fabricating high density devices like advanced ULSI (ultra-large scale integration) devices, the borophosphosilicate glass (BPSG) film has been widely used as the pre-metal dielectric (PMD), inter-layer dielectric (ILD), or inter-metal dielectric (IMD) layers to achieve global planarization. A. Tissier et al. introduced the characteristics of dielectric materials as pre-metal layers in their work "Planarization of Pre-metal and Metal Levels for 0.5 .mu.m and 0.35 .mu.m logic CMOS Processes" (Proceedings on Advanced Metallization for ULSI Applications, p. 341, 1994). They addressed that in developing 0.35 micrometer CMOS logic processes, it has become clear that a strong increase in the number of interconnect levels is mandatory, in order to use the tremendous transistor density available in the silicon. The borophosphosilicate glass film formed by tetra-ethyl-ortho-silicate (TEOS) are introduced as one of the choices of pre-metal dielectric layers in fabricating advanced ULSI devices.
However, the high temperature anneal after opening the contact hole will induce the borophosphosilicate glass film reflowing to form an overhang structure at the top of contact holes. In the U.S. Pat. No. 5,554,565 titled "Modified BP-TEOS Tungsten-Plug Contact Process" to J. J. Liaw et al., the problem of void formation during metallization is illustrated. In the introduction of prior art processes in their invention, a rapid-thermal-annealing (RTA) was performed to activate implanted ions. A borophosphosilicate glass film was flowed at contact hole edges and severely encroach into the contact opening under high temperature. The encroachment of the borophosphosilicate glass film into the contact opening causes a restriction to the filling of the contact hole by the tungsten leaving a void in the center. The formation of voids causes the thinning of the filling tungsten plug and increases the resistance of interconnect wires. The thin tungsten walls surrounding the void cause a potential problem of subsequent electrical failure.
In addition to the problem of increased resistance of interconnect wires and electrical failures under void formation, another possible damage to the interconnection structure comes from the volcano formation. For typical tungsten-plug technology, the adhesion of pure tungsten to the sides of the silicon oxide contact hole is poor and the applying of an adhesion layer like titanium nitride is needed before tungsten deposition. The precursor of tungsten hexafluoride (WF.sub.6) will penetrate the titanium nitride film and react with underlying titanium layer to form the by-product TiF.sub.3. The formation of the non-adherent TiF.sub.3 layer and TiF.sub.3 gas causes the tungsten layer or the titanium nitride layer to peel and damages the devices, the disastrous effect being known as tungsten volcano effect.
C. R. Chang et al. described the volcano effect in the U.S. Pat. No. 5,672,543 titled. "Volcano Defect-Free Tungsten Plug". They introduced that the nucleation step of the tungsten chemical vapor deposition process has a WF.sub.6 gas rich chamber condition. The WF.sub.6 gas penetrates through the titanium layer and react with the titanium molecules to form TiF.sub.3 gas. The continuous out-gassing of TiF.sub.3 through the deposited Tungsten film will create a mountain-shaped opening on top of the tungsten film and the defect is the so-called volcano defect.
Therefore, a method of solving the problem caused by the void formation and the volcano defect is highly needed in the field silicon processing. A void-free and volcano-free process must be provided for fabricating defect-free advanced ULSI devices.